Vol 5 Issue 1 September 2017-August 2018
MAHALAKSHMI M, P.THIRUVALAR SELVAN
Abstract:The present scenario of the circuit subthreshold CMOS logic circuits is becoming increasingly popular energy- constrained applications where high performance is not required. Minimum energy consumption of digital logic circuits can be obtained by operating in the subthreshold regime. However, in this regime process variations can result in up to order of magnitude variations in ION / IOFF ratios leading to timing errors, which can have a destructive effect on the functionality of the subthreshold circuits. These timing errors become more frequent in scaled technology nodes where process variations are highly prevalent. Therefore, mechanisms to mitigate these timing errors while minimizing the energy consumption are required. In this proposed work, Low power subthreshold logic circuits using adaptive feedback equalizer circuit is designed. The adaptive equalizer technique is used with a sequential digital logic to mitigate the process variation effects and reduce the dominant leakage energy components in the subthreshold digital logic circuits. The performance of the proper circuit is evaluated for different input voltages, other work for 4 bit Ripple Carry Adder in designed using to the logic gate size and power is discussed in the simulation is successfully in verified with the help of Microwind and Dsch tool.
Keywords:Adaptive Feedback equalizer, Low power subthreshold, variable threshold inverter, Ripple Carry Adder.
Title:Design and analysis of RCA in Subthreshold Logic Circuits Using AFE
Author:MAHALAKSHMI M, P.THIRUVALAR SELVAN
ISSN 2394-9678
International Journal of Novel Research in Electrical and Mechanical Engineering
Novelty Journals